Circuit designs are typically system level designs on a system on chip (SOC). In system level designs board-level bus analysis is usually accomplished through the use of connectors and cables which attach to the system bus, allowing devices (such as logic analyzers, digital oscilliscopes, etc.) to sample bus transactions over a given time period. As system-level board designs have migrated to system on chip (SOC) designs, there should exist a similar mechanism to perform at speed on-chip bus performance analysis.
There are two conventional approaches to accomplishing a similar task:                1. Internal logic for on-chip analysis has been implemented in some processor designs, however, those implementations are limited to tracking logic activity within the processor core. Those versions lack the capability of monitoring any bus activity external to the processor, therefore, facilitating an alternate means of monitoring if a processor's transactions transition correctly outside of the processor core. In processor-embedded SOCs where much activity is performed external (and sometimes independent) of the processor, there needs to exist a method of verifying this.        2. In other on-chip implementations, internal bus signals are wired to off-chip pins. An external analysis device is then attached and samples the data from the off-chip pins.        
However, for this mechanism to attach to all of the necessary internal signals and allow full flexibility in the types of bus monitoring that can be performed, the design could become quite large. As SOC designs are starting to utilize more die area, fitting such an oversized design block into the SOC layout becomes quite a challenge for placement and wiring, especially where contiguous whitespace is virtually nonexistent. Another problem would be that a design of such a large fixed-size mechanism does not lend itself well to implementations in larger SOC designs where bus traffic from a few additional devices may require monitoring. This limits the mechanism's scalability, possibly requiring a redesign of the performance-monitoring mechanism specifically for designs where functionality may have increased.
Accordingly, what is needed is a system and method for monitoring bus activity in an SOC that is scalable and does not add significantly to the die size or cost with the SOC. The present invention addresses such a need.